1. Field of the Invention
The present invention relates to fabricating semiconductor devices and more particularly to forming high quality oxide layers for semiconductor devices.
2. Description of Previous Art
As advances in processing technology allow ever increasing number of integrated devices to be fabricated on a single integrated circuit (IC), fabricating these integrated devices with consistent electrical properties is a constant struggle. Strict guidelines and tight tolerances are setup for fabricating facilities in efforts to produce integrated devices with reproducible electrical properties. However, even with the strict guidelines and the tight tolerances, there are still many problems with the processing technologies that are currently in use.
For example, when a metal oxide silicon (MOS) transistor is fabricated, the gate of the transistor is first formed on the silicon substrate. Once the gate is formed, the source and the drain of the MOS transistor are formed. In forming the gate of the MOS transistor, a gate oxide is first grown over the silicon substrate. Next, a gate layer is formed over the gate oxide. A screen oxide is applied over the areas surrounding the gate oxide and the gate to protect the gate stack of the MOS transistor from later processing in the formation of the source and drain. One problem that is prevalent when applying the screen oxide to the gate stack of the MOS transistor is thickening of the gate oxide.
Thickening of the gate oxide occurs at the stack edges of the MOS transistor. The thickened gate oxide encroaches the gate layer by oxidizing portions of the gate. In fabricating single gate MOS transistors, thickening of the gate oxide cause variations in threshold voltages and drive current when slight variations in gate length and processing conditions occur. These slight variations in gate length and processing often occur during fabrication. Threshold voltage and drive current variations cause the MOS transistors to have inconsistent activation voltages. Thus, the electrical properties of these MOS transistors fluctuate and are inconsistent with each other.
In fabricating multiple gate transistors such as electrically erasable programmable read only memories (EEPROM's) having a floating gate and a control gate, the thickening of the gate oxide has the undesirable effect of reducing the coupling between the floating gate and the control gate which can cause programming and erasing errors. Other undesirable effects include increasing the barrier to tunneling or hot carrier injection between the source/channel/drain regions and the floating gate. Given that program and erase operations of EEPROM's rely on carriers passing through a tunnel oxide so that the carriers can either be trapped or removed, the effects of thickening the tunneling oxide increase program and erase operations. Additionally, without a uniformly formed tunneling oxide, the reliability of the EEPROM's will suffer. Tunnel oxide breakdown will occur more often causing the EEPROM's to fail. The thickening of the tunneling oxide also changes with slight variations in gate lengths and processing conditions that often occur during processing of the nonvolatile memory transistors.
The effects of the thickening oxide are even more pronounced and becomes proportionally greater as the gate lengths of the MOS transistors are scaled smaller. As current advances in processing technology allow ever increasing number of smaller scaled integrated devices to be fabricated on a single IC, the problem of thickening oxide becomes more apparent. A high quality oxide layer of uniform thickness is important if the MOS transistors are to be scaled smaller.
Therefore, it is desirable to provide a method of forming a high quality oxide layer for silicon gates to produce MOS devices that possesses more consistent electrical properties and is less sensitive to process variations for better performing and more reliably operating MOS circuits.